Emerging Trends in RF Packaging

Emerging Trends in RF Packaging

As the downscaling of transistor size in semiconductors becomes more challenging, research and development efforts are now approaching the limits set by Moore’s Law. This is a result of the physical challenges introduced as the industry approaches an era of smaller technology nodes. With that, the need to further reduce the sizes of transistors is on a constant increase, and this calls for the development of new products by IC manufacturers. 

To overcome these challenges, two paths are now set, and they are More Moore, which is focused on downscaling transistor size, irrespective of high cost. The focus of this approach is on integrating functionalities within a single chip and this process is called System-on-chip integration. On the other hand, the second approach relies on the integration of functionalities by packing various chips. 

This article will take you through some of the emerging trends in RF and microwave packing. You’ll learn about key processes like Flip-Chip packaging, System-on-chip, Fan-out packaging, 3D packing, and System-in-package. Continue reading for more information. 

Process Technologies

Process technologies are mostly grouped based on their footprint and I/O count. The technologies applied for those with low footprint and low I/O count are Fan-Out Wafer-Level-Packages and Flip-Chip Chip-Scale Packages. These packages are widely applied in electronic components for wireless and mobile communications. Both technologies can also be applied in cases requiring a bigger footprint and higher I/O count. 

Other options include SiP designs, and 3D integrations are also used in different applications. We’ll go through each of these process technologies below:


This is an approach that continues to grow in popularity, and it involves the monolithic combination of different modules, including logic and memory, on a single chip. The importance of this combination is that it makes the system to be very lightweight and compact. Even though this trend is growing in popularity, it’s worth noting that there are a few limitations associated with it. This includes fabrication and test costs, the huge number of mask steps, long design times, dissimilar process technologies, and mixed-signal processing complexities. 

Flip-Chip Technology

Packages like lead frame-based solutions that were mostly applied in the 1980s had a couple of disadvantages that altered their performance. Today, Flip chip packing offers more benefits, especially when it comes to performance. The main feature they offer is the active area within the chip that directly faces that of another chip. 

Key advantages of the wafer-level chip scale packages that make them better than conventional packing technologies include lighter systems, simpler structure, smaller form factor, and higher cost efficiency. 

System in Package

This is an integration consisting of many dissimilar or similar chips arranged on a common substrate. They are mostly placed in close proximity to each other, and in some instances, they are stacked vertically. This approach offers many benefits, especially when it comes to simplifying design requirements at a reduced cost. This also includes enhanced lead time while maintaining high levels of integration. 

Fan-Out Packaging

This was first introduced in 2001 by Infineon, and it was called embedded wafer-level BGA as at then. The benefit of this packaging is that it doesn’t require package substrate or wire bonding, thereby bringing about a significant reduction in the cost of production and further increasing the performance and density of the packaging. Another thing to note is that this technology is also utilized in multi-chip integration applications, which is also vital for integrated systems-in-package designs. 

There are three process technologies that are used for this purpose, and they include the following: the die-first, face-down approach, which is the most popular one and is molded with the aid of compression molding and placed on a release layer before being redistributed with the aid of electroplating and photolithography processes. 

The die first, face-up is the second approach and it aims at removing debonding steps. Copper contact pads are used to equip the die. Lastly is the RDL first, die last approach, which relies on AMKOR SWIFT technology. 

3D Packaging

This is another emerging technology to note, and even though the horizontal integration of functionalities is difficult, vertical integration is now possible and continues to grow in popularity. There are two approaches that are applied to achieve this, and they are the package-on-package stacking and wire bond-based stacking. 

Wire bonded stacks are very common and used in memory stacking, while package on package processes is applied when placing processes in close proximity to memory. This is particularly a vital approach for use in cases where the footprint is rather limited, like in smartphones.

Roadmap for Heterogeneous Integration 

The aim of this roadmap is to further enhance technological advances in the next few years. It helps to stimulate and enhance collaboration between industry partners to further reduce the time for development cycles. This type of integration is further gaining more traction, and this is because Moore’s Law ending causes higher costs for downscaling the size of transistor. 

Heterogeneous integration is basically the integration of separately manufactured components to a greater assembly level. The aim is to offer improved operational characteristics and enhance functionality. With that, it makes it possible for small functional components to be packaged when building system level functionality. Another reason that calls for the need for further integration is the growing need for its application within diverse industries. 

Some key technological solutions that allow the application of these technologies include artificial intelligence and high performance computing, 5G and smartphone technology, and even in automotive applications. 


The need for effective miniaturization of electrical components cannot be overemphasized, and we have highlighted some cutting-edge trends that are currently growing in popularity. We have also highlighted the two approaches being utilized which are More Moore, and More than Moore approaches. 

There are various key process technologies that are making waves within the electronic industry, and they include Fan-out packaging, 3D integration, system-in-package, system-on-chip, and flip-chip technology. All of these have been highlighted above, leading into the heterogeneous integration roadmap for the nearest future. 

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